Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device

ABSTRACT

A method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device by which a gettering ability can be given to an epitaxial wafer in which the formation of BMD is not able to be expected in both low- and high-temperature device manufacturing processes, with the manufacturing processes being lower and higher than 1,050° C. in temperature, and has a specific resistance of ≧10 mΩ·cm. When this method is used, such BMD that is sufficient to obtain gettering can be formed in both the low- and high-temperature processes, with the manufacturing processes being lower and higher than 1,050° C. in temperature, even in the epitaxial wafer having a specific resistance of ≧10 mΩ·cm by performing low-temperature heat treatment at 650˜900° C. before starting epitaxial film formation, by selecting the heat-treating time in accordance with the process temperature in the device manufacturing processes and heavy-metal contaminants which are mixed in during the device manufacturing processes can be gettered sufficiently. Therefore, the characteristic deterioration of a device can be prevented and the yield of the device can be improved.

TECHNICAL FIELD

The present invention relates to a manufacturing method for grantinggettering capabilities to a silicon epitaxial wafer used as a substratefor various semiconductor devices, and to a semiconductor siliconepitaxial wafer and semiconductor device manufacturing method, by whichBMD (Bulk Micro Defect) required for gettering is formed in a wafer in asemiconductor device manufacturing process, which passes through a 1050°C. or lower temperature process flow, or a 1050° C. or highertemperature process flow in accordance with either performing apredetermined low-temperature heat treatment on a pulled siliconsingle-crystal ingot, or performing a predetermined low-temperature heattreatment prior to the formation of an epitaxial layer, enabling thedemonstration of a sufficient IG (Intrinsic Gettering) effect, andenhanced device yield.

BACKGROUND ART

In a ULSI device manufacturing process, a variety of process flows areperformed in accordance with the constitution of a device. For example,in a high-temperature heat treatment process or the like, heavy metalimpurities, typified by Fe, Ni, Cu, can cause the formation of defectsor an energy level near the surface of a wafer resulting in thedegradation of device characteristics. These heavy metal impurities musttherefore be removed from the vicinity of the wafer surface, and inorder to achieve this, IG (Intrinsic Gettering) and various EG(Extrinsic Gettering) gettering techniques are used.

Generally, oxygen precipitate nuclei, which make impurity getteringpossible, are scattered about in large numbers in a silicon singlecrystal grown using the Czochralski method or the magnetic Czochralskimethod (hereinafter referred to as the CZ method). These oxygenprecipitate nuclei are introduced during the process of growing asilicon single crystal, and the higher the oxygen concentration, themore numerous the oxygen precipitate nuclei.

In a conventional high-temperature device process, having a Well Driveprocess, because oxygen precipitation occurs relatively easily duringdevice process heat treatment, forming sufficient BMD for gettering inbulk, NIG (Natural IG), DZ(Denuded Zone)-IG gettering has come intowidespread use.

In the device process of the future, it has become clear thatmanufacturers will promote low-temperature processes that strive for yethigher levels of integration, and make use of high energy ionimplantation. In that case, the in-process formation of BMD is expectedto become a problem because of the move to low-temperature processing.

Therefore, in a low-temperature process, it is difficult to achieve anadequate IG effect as with a high-temperature process. Further, it isbelieved that even with a low-temperature process, it will be hard toavoid heavy metal impurities from high energy ion implantation and otherfactors, making gettering technology imperative.

Meanwhile, higher integration levels require that quality be increasedeven further in the near surface region of the wafer. Since, unlike aCZ-Si wafer, there are absolutely no Grown-in defects in an epitaxiallayer, an epitaxial wafer has extremely high quality surface integrity.But until now, the use of epitaxial wafers has been limited by costfactors.

However, due to the problem of Grown-in defects, there is an extremelyhigh likelihood that epitaxial wafers will be utilized in earnest ineven higher integration next-generation devices (64MB, 256MB DRAM era).And epitaxial wafers are viewed as being the most likely candidates for12-inch wafers as well.

To date, DZ-IG processing has been widely used to enhance the quality ofthe ordinary CZ-Si wafer. With this approach, a two-stage hightemperature and low temperature heat treatment is performed. First,oxygen near the surface of a wafer is diffused toward the outside,interstitial oxygen, which constitutes the nuclei of microdefects, isreduced, and a DZ(Denuded Zone) layer, in which there are no defects inthe device active area, is formed by subjecting a wafer tohigh-temperature heat treatment at between around 1100° C. and 1200° C.Thereafter, oxygen precipitate nuclei are formed in the wafer bulk vialow-temperature heat treatment at between 600° C. and 900° C. However,with DZ-IG processing, grown-in defects exist in the device active area.

If this wafer is subjected to a high-temperature device process, oxygenprecipitate nuclei grow into oxygen precipitates in accordance with thehigh-temperature heat treatment of the process, and a sufficient IGeffect is exhibited. But with DZ-IG processing, problems arise in astate-of-the-art device process, such as residual Grown-in defects inthe device active area, and the lack of in-process growth of sufficientoxygen precipitates in low-temperature device processing.

If the oxygen precipitation behavior of p/p++, p/p+, p/p− epitaxialwafers is compared, in a p/p++ epitaxial wafer, that has a highconcentration of B in the substrate (substrate resistivity <10 mΩ·cm),oxygen precipitation occurs extremely easily in accordance with theeffect of the high concentration of B. As shown in FIG. 3, sufficientBMD for gettering are formed, and an adequate IG effect can be expectedeven in a low-temperature process, and even in a low oxygenconcentration substrate ([Oi]=12×10¹⁷ atoms/cm³ old ASTM, hereinafteromitted) for an epitaxial wafer with a substrate resistivity of lessthan 6 mΩ·cm, and in a high oxygen concentration substrate ([Oi]=15×10¹⁷atoms/cm³) for an epitaxial wafer with a substrate resistivity ofbetween 8˜10 mΩ·cm.

Furthermore, FIG. 3 shows the results of selectively etching (5 minuteWright Etch) a wafer, and measuring BMD density using an opticalmicroscope after using 8-inch outside diameter, p(100)B-doped substrateswith initial oxygen concentrations of 12×10¹⁷ atoms/cm³ and 15×10¹⁷atoms/cm³ to prepare a variety of epitaxial wafers with differentsubstrate resistivity, and subjecting these wafers to the pattern oflow-temperature process heat simulation shown in FIG. 1.

Further, the results of comparing the oxygen precipitation behavior ofan epitaxial wafer and a polished wafer in a high-temperature processflow are shown in FIG. 4. FIG. 4 shows the results of selectivelyetching (5 minute Wright Etch) a wafer, and using an optical microscopeto measure BMD density after utilizing 8-inch outside diameter,p(100)B-doped substrates with two types of substrate resistivity, 10˜20mΩ·cm(p+) and 10Ω·cm(p−), to prepare mirror polished wafers with initialoxygen concentrations varying in the range of 11˜17×10¹⁷ atoms/cm³, andepitaxial wafers, the epitaxial layers of which were grown on wafersfrom the same lot as the mirror polished wafers, and subjecting thesewafers to the pattern of high-temperature process heat simulation shownin FIG. 2.

When a mirror polished wafer is subjected to a high-temperature deviceprocess, oxygen precipitate nuclei grow to become oxygen precipitates inaccordance with the high temperature heat treatments in the process,exhibiting an adequate IG effect.

Conversely, with an epitaxial wafer having resistivity of 10 mΩ·cm orhigher, oxygen precipitate nuclei shrink or disappear as a result of thehigh-temperature heat histories at epitaxial growth, and oxygenprecipitation is apparently suppressed considerably compared to that ofa mirror polished wafer. It became clear that little if any BMD isformed, and the IG effect cannot be expected with an epitaxial waferhaving substrate resistivity of 10 mΩ·cm or higher in either alow-temperature process or a high-temperature process, even when asubstrate with a fairly high oxygen concentration is utilized.

Methods for performing pre-epitaxial growth heat treatment in order toachieve a sufficient IG effect have already been studied. In H. Tsuya etal.: APPI. Phys. Lett. 36 (1980) 658, heat treatment conditions callingfor temperatures of between 620° C. to 1150° C. for between 16 hours and64 hours in an oxygen atmosphere were studied, and indicated that heattreatment at 820° C. for 16 hours is effective for gettering. However,the evaluation of BMD was performed after heat treatment at 1140° C. for2 hours on the assumption of a high temperature process, and the effectof the low-temperature process was not clear. There was also the problemthat a heat treatment time of 16 hours or more is extremely long.

Further, Japanese Patent Publication No. 4-56800 reports a 2-stage heattreatment method, wherein, prior to epitaxial growth, a hightemperatureheat treatment (1000˜1100° C.) is added following a low-temperature heattreatment (500˜900° C.). But this is a low temperature + hightemperature 2-step heat treatment, a high cost, long duration heattreatment, and slippage and contamination problems associated withhigh-temperature heat treatment must also be considered.

Japanese Patent Laid-open No. 8-97220 proposes a method, wherein, duringthe process in which the temperature is increased in the epitaxialgrowth process, either the rate of increase in a temperature range offrom 800° C. to 1000° C. is less than 15° C./min, or an arbitrarytemperature is maintained for between 5˜100 minutes. With this method,there is a clear drop in epitaxial throughput, and this method is alsoproblematic in that the current situation requires the low cost, stablemanufacture of epitaxial wafers.

As described above, epitaxial wafers are viewed as prime candidates foruse as next-generation device wafers, but in the past it was difficultto achieve a sufficient IG effect in an epitaxial wafer, especially ap-type (B-doped) wafer having a substrate resistivity of 10 mΩ·cm orhigher, using a low-temperature device process, even when a substratewith a high oxygen concentration was used.

DISCLOSURE OF THE INVENTION

With the foregoing epitaxial wafer gettering (IG) problems in view, anobject of the present invention is to provide a semiconductor siliconepitaxial wafer and semiconductor device manufacturing method, which canexhibit a sufficient gettering effect (IG), and enhance device yield inboth a device manufacturing process according to a low-temperatureprocess flow of under 1050° C., and a device manufacturing processaccording to a high-temperature process flow of over 1050° C.

Similarly, a further object of the present invention is to provide asemiconductor silicon epitaial wafer and semiconductor devicemanufacturing method, which simplifies processing as much as possible inorder to reduce costs, and which can exhibit a sufficient getteringeffect (IG), and enhance device yield even in a device manufacturingprocess, wherein the only processing is at the pulling of the siliconsingle crystal ingot using the CZ method, without the carrying out ofany process that can be expected to produce a post-wafering EG effect inthe wafer.

The inventors, having as an object a semiconductor silicon epitaxialwafer capable of demonstrating a sufficient gettering effect (IG) inboth a low-temperature device manufacturing process of under 1050° C.,as well as in a device manufacturing process according to ahigh-temperature process flow of over 1050° C., conducted variousstudies aimed at performing a variety of low-temperature heat treatmentsprior to growing an epitaxial layer. As a result, the inventors broughtthe present invention to completion based on the knowledge that if alow-temperature heat treatment of between 650° C. and 900° C. isperformed prior to the growth of an epitaxial layer by selecting a heattreatment time in accordance with the processing temperature of a devicemanufacturing process, even in an epitaxial wafer with a resistivity of10 mΩ·cm or higher, it is possible to achieve a sufficient gettering(IG) effect in both a low-temperature and a high-temperature deviceprocess having 1050° C. as the border temperature.

That is, the inventors discovered that sufficient BMD for gettering isformed in the heat treatment processes of a low-temperature deviceprocess, and a semiconductor silicon epitaxial wafer having sufficientIG capabilities can be achieved in a p-type (B-doped) CZ-Si wafer with aresistivity of 10 mΩ·cm or higher, in accordance with growing anepitaxial layer after annealing the wafer at between 650° C. and 900°C., preferably for 3 hours or longer, preferably in an oxygen ornitrogen atmosphere, or in a gas mixture thereof, prior to epitaxiallayer growth.

Further, the inventors similarly discovered that sufficient BMD forgettering is formed in the heat treatment processes of ahigh-temperature device process, and a semiconductor silicon epitaxialwafer having a sufficient IG effect can be achieved, and device yieldenhanced in accordance with growing an epitaxial layer after annealingthe wafer at between 700° C. and 900° C., preferably for less than 3hours in the above-described atmosphere prior to epitaxial layer growth.

Further, the inventors propose a semiconductor device manufacturingmethod, which applies to a semiconductor silicon epitaxial wafer aprocess flow that accords with the constitution of a device, thissemiconductor device manufacturing method making possible the formationof sufficient BMD required for gettering, the demonstration ofsufficient IG capabilities, and the enhancement of device yield inaccordance with subjecting a sliced p-type (B-doped) CZ-Si wafer with aresistivity of 10 mΩ·cm or higher either to a heat treatment at atemperature of between 650° C. and 900° C., preferable for 3 hours orlonger, or to a heat treatment at a temperature of between 700° C. and900° C., preferable for less than 3 hours, and thereafter applying theabove-mentioned 1050° C. or lower low-temperature process flow, or theabove-mentioned 1050° C. or higher high-temperature process flow to asemiconductor silicon epitaxial wafer on which an epitaxial layer hasbeen grown.

Furthermore, having as an object a semiconductor silicon epitaxial wafercapable of demonstrating a sufficient gettering effect (IG) in both alow-temperature device manufacturing process of under 1050° C., as wellas in a device manufacturing process according to a high-temperatureprocess flow of over 1050° C., the inventors conducted various studiesaimed at granting gettering capabilities to an as-pulled silicon singlecrystal ingot itself. As a result, the inventors brought the presentinvention to completion based on the knowledge that if the same means asthose described above can be applied to the heat treatment of a wafer,and a low-temperature heat treatment of between 650° C. and 900° C. isperformed following the pulling of a silicon single crystal ingot usingthe CZ method by selecting a heat treatment time in accordance with theprocess temperature of a device manufacturing process, it is possible toachieve a sufficient gettering (IG) effect in both a low-temperature anda high-temperature device process having 1050° C. as the bordertemperature even in an epitaxial wafer with a resistivity of 10 mΩ·cm orhigher on which an epitaxial layer has been grown, without performing aprocess that can be expected to produce an EG effect after the ingot hasbeen sliced into silicon wafers.

Therefore, the present invention grants gettering capabilities that arenot lost even under the influence of epitaxial layer growth heathysteresis, by simply performing low-temperature heat treatment on asilicon single crystal ingot pulled using the CZ method by controllingthe B concentration for achieving a p-type (B-doped) CZ-Si wafer with aresistivity of 10 mΩ·cm or higher, enabling the realization of asemiconductor silicon epitaxial wafer, in which sufficient BMD forgettering is formed in the annealing process of a device process, andwhich has sufficient IG capabilities for a variety of impurities, andenabling processing to be simplified by eliminating the need to performany processing that could be expected to produce a post-wafering EGeffect.

That is, the present invention is a semiconductor device manufacturingmethod, which applies to a semiconductor silicon epitaxial wafer aprocess flow that accords with the constitution of a device, thissemiconductor device manufacturing method making possible the formationof sufficient BMD required for gettering, the demonstration ofsufficient IG capabilities, and the enhancement of device yield inaccordance with subjecting a silicon single crystal ingot, pulled usingthe CZ method by controlling the B concentration for achieving a p-type(B-doped) CZ-Si wafer with a resistivity of 10 mΩ·cm or higher, eitherto a heat treatment at a temperature of between 650° C. and 900° C. for3 hours or longer, or to a heat treatment at a temperature of between700° C. and 900° C., preferably for less than 3 hours, and thereafter,without performing a process that could be expected to produce apost-wafering EG effect, applying either the above-mentioned 1050° C. orlower low-temperature process flow, or the above-mentioned 1050° C. orhigher high-temperature process flow to a semiconductor siliconepitaxial wafer, which has been mirror polished on either one side ortwo sides, and has had an epitaxial layer grown on a predeterminedsurface via a vapor phase growth method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing a heat simulation pattern of a low-temperatureprocess utilized in experiments of the present invention;

FIG. 2 is a graph showing a heat simulation pattern of ahigh-temperature process, which is a semiconductor device processutilized in the experiments;

FIG. 3 is a graph of initial oxygen concentrations and BMD densities,showing the results of applying the low-temperature process heatsimulation of FIG. 1 to a variety of 8-inch substrate epitaxial wafers,having different initial oxygen concentrations and resistivity,following which the wafers were selectively etched and BMD density wasmeasured using an optical microscope;

FIG. 4 is a graph of initial oxygen concentrations and BMD densities,showing the results of preparing mirror polished wafers from 8-inchp(100)B-doped CZ-Si substrates with two types of substrate resistivity,10˜20 mΩ·cm(p+) and 10Ω·cm(p−), and different initial oxygenconcentrations, and epitaxial wafers, which had 3 μm thick epitaxiallayers grown on wafers from the same lot as the mirror polished wafers,and subjecting these wafers to the high-temperature process heatsimulation of FIG. 2, following which the wafers were selectively etched(5 minute Wright Etch), and BMD density was measured using an opticalmicroscope;

FIG. 5 is a graph of initial oxygen concentrations and BMD densities,showing the results of applying various 6-inch substrate wafers withdifferent initial oxygen concentrations to a variety of heat treatments,manufacturing epitaxial wafers, and thereafter subjecting these wafersto the low-temperature process heat simulation of FIG. 1, after whichthe wafers were selectively etched, and BMD density was measured usingan optical microscope;

FIG. 6 is a graph of BMD densities and pre-epitaxial growth heattreatment times under a variety of conditions, showing the results ofsubjecting wafers from 8-inch p(100)B-doped CZ-Si substrates with aninitial oxygen concentration of 15×10¹⁷ atoms/cm³ (old ASTM) tolow-temperature heat treatments under a variety of conditions in anitrogen atmosphere prior to epitaxial growth, then manufacturingepitaxial wafers by growing thereon 3 μm thick epitaxial layers, andthereafter, subjecting these wafers to the high-temperature process heatsimulation of FIG. 2, selectively etching the wafers (5 minute WrightEtch), and using an optical microscope to measure BMD density;

FIG. 7 is a graph showing the results of applying a low-temperatureprocess heat treatment to an embodiment, and thereafter measuring thegeneration lifetime in accordance with the MOS-Ct method; and

FIG. 8 is a graph of initial oxygen concentrations and BMD densities,showing the results of subjecting wafers from 8-inch p(100) B-doped(resistivity of 10Ω·cm) CZ-Si substrates with different initial oxygenconcentrations to heat treatment at 800° C. for 2 hours, and thereafter,manufacturing epitaxial wafers by growing thereon 3 μm thick epitaxiallayers, subjecting these epitaxial wafers to the high-temperatureprocess flow heat simulation of FIG. 2, selectively etching (5 minuteWright etch) the wafers, and measuring BMD using an optical microscope.

BEST MODE FOR CARRYING OUT THE INVENTION

As for the present invention, the inventors performed a variety of heattreatments on a p-type CZ-Si wafer prior to epitaxial growth, then grewan epitaaial layer, subjected the epitaxial wafer to low-temperatureprocess heat simulation of the pattern shown in FIG. 1, and studied BMDgeneration behavior. As a result, the inventors clarified that asufficient gettering (IG) effect can be achieved in a low-temperaturedevice process as well, even with an epitaxial wafer having aresistivity of 10 mΩ·cm or higher, if pre-epitaxial growthlow-temperature heat treatment is performed using conditions of between650° C. and 900° C., preferably for 3 hours or longer. The inventorsalso studied BMD generation behavior after subjecting an epitaxial waferto the high-temperature process flow heat simulation of the patternshown in FIG. 2 (See FIG. 4). As a result, the inventors clarified thata sufficient gettering (IG) effect can be achieved in a high-temperaturedevice process even in an epitaxial wafer having a resistivity of 10mΩ·cm or higher, if pre-epitaxial growth low-temperature heat treatmentis performed using conditions of between 700° C. and 900° C., preferablyfor less than 3 hours.

The present invention is characterized in that a 1-step low-temperaturewafer heat treatment is performed prior to an epitaxial growth process,and it is a novel invention, which enables low-cost, volume waferprocessing, is capable of being applied to either a low-temperatureprocess or a high-temperature process, and differs from all theabove-mentioned conventional processing methods as to substrate oxygenconcentration, and resistivity, and heat treatment temperature, time,and atmosphere.

Further, the inventors performed a variety of low-temperature heattreatments on a silicon single crystal ingot pulled using a CZ method bycontrolling the concentration of B, following which they sliced, mirrorpolished, and grew an epitaxial layer on the p-type CZ-Si wafers,subjected the epitaxial wafers to low-temperature process heatsimulation of the pattern shown in FIG. 1, and studied BMD generationbehavior. As a result, the inventors confirmed that a sufficientgettering (IG) effect can be achieved in a low-temperature deviceprocess as well, even with an epitaxial wafer having a resistivity of 10mΩ·cm or higher, without performing a process that can be expected toproduce a post-wafering EG effect, if low-temperature heat treatment isperformed on a pulled ingot using conditions of between 650° C. and 900°C., preferably for 3 hours or longer. The inventors also studied BMDgeneration behavior after subjecting an epitaxial wafer tohigh-temperature process flow heat simulation of the pattern shown inFIG. 2 (See FIG. 6). As a result, the inventors confirmed that asufficient gettering (IG) effect can similarly be achieved with ahigh-temperature device process, even in an epitaxial wafer having aresistivity of 10 mΩ·cm or higher, if low-temperature heat treatment isperformed on a pulled ingot using conditions of between 700° C. and 900°C., preferably for less than 3 hours. That is, the inventors confirmedthat all the embodiments, such as the below-described heat treatmentconditions for a wafer, are the same as the heat treatment for a singlecrystal ingot.

In the present invention, the reason that substrate resistivity is made10 mΩ·cm or higher is because, at less than 10 mΩ·cm, as alreadyexplained, oxygen precipitation is abnormally accelerated by the effectof a high concentration of B, and because gettering-sufficient BMD,which is not affected by the heat histories at epitaxial deposition, isformed at an extremely early stage of a low-temperature process withoutpre-epitaxial growth heat treatment. In a 10 mΩ·cm or higher substrate,since oxygen precipitation is significantly suppressed by the heathistories during epitaxial growth, pre-epitaxial growth heat treatmentin accordance with the present invention is essential for achievingsufficient BMD.

In the present invention, with regard to the oxygen concentration of asubstrate, 12×10¹⁷ atoms/cm³ or more is desirable. An oxygenconcentration lower than 12×10¹⁷ atoms/cm³ does not achieve sufficientBMD at heat treatment conditions of between 650° C. and 900° C. for 3hours or longer. As shown in FIG. 5, sufficient BMD was observed in asubstrate of 12×10¹⁷ atoms/cm³ or more following low-temperature processheat simulation of the pattern shown in FIG. 1.

In the present invention, the heat treatment temperature applied to awafer slated for low-temperature processing is set at between 650° C.and 900° C. because at less than 650° C., although oxygen precipitatenuclei are grown to sizes that will not shrink under thehigh-temperature heat histories during the growth of an epitaxial layer,these temperatures are not desirable because of the long heat treatmenttime required. When the heat treatment temperature exceeds 900° C., thetemperature is too hot, oxygen precipitate nuclei of sufficient densityare not grown, and the effect thereof is not achieved.

It is desirable that the heat treatment temperature applied to a waferslated for low-temperature processing be applied for more than 3 hoursat the above-described temperature conditions to achieve BMD ofsufficient density, 5×10⁴ defects/cm² or higher, for gettering even in alow-temperature process.

In the present invention, the heat treatment temperature applied to awafer slated for high-temperature processing is set at between 700° C.and 900° C. because at under 700° C., although oxygen precipitate nucleiare grown to sizes that will not shrink under the high-temperature heathistories of epitaxial layer growth, these temperatures are notdesirable because of the long heat treatment time required. When theheat treatment temperature exceeds 900° C., the temperature is too hot,oxygen precipitate nuclei of sufficient density are not grown, and theeffect thereof is not achieved.

The heat treatment temperature applied to a wafer slated forhigh-temperature processing is applied for less than 3 hours even in a700° C. heat treatment, and is set at less than 3 hours to achieve BMDof sufficient density (>5×10⁴ defects/cm²) for gettering.

Furthermore, in an epitaxial wafer, in which BMD of 5×10⁵ defects/cm² orhigher had been generated in the heat simulation of a high-temperatureprocess flow, slippage dislocation caused by excess oxygen precipitationwas observed in the center portion of the wafer following heatsimulation. This slippage dislocation is known to adversely affectdevice characteristics. Therefore, due to the problem of in-processslippage dislocation generation, it has become clear that, in the caseof a high-temperature device process, it is necessary to make BMDdensity less than 5×10⁵ defects/cm², and more preferably, less than1×10⁵ defects/cm².

Even when heat treatment time was less than 3 hours, with a substratehaving an oxygen concentration of 15×10¹⁷ atoms/cm³ (old ASTM), morethan 5×10⁵ defects/cm² of BMD was formed following heat simulation ofwafers that were subjected to pre-epitaxial growth low-temperature heattreatments at 800° C. for 2 hours and 3 hours, and slippage dislocationwas also observed in the center portion of the wafers. But, in thiscase, BMD density can be optimized by adjusting the oxygen concentrationof the substrate, and as shown in FIG. 8, it was confirmed that theoptimum BMD density can be achieved, and the generation of slippagedislocation prevented by reducing the substrate oxygen concentration.The desirable substrate oxygen concentration is 10˜15×10¹⁷ atoms/cm³(old ASTM).

As for the atmosphere, in an oxygen atmosphere at a temperature of 1000°C., the injection of an interstitial silicon atom into the bulk occursin line with the formation of a surface oxide film, and oxygenprecipitation is suppressed more than in a non-oxidizing atmosphere. Butat under 900° C., the growth of an oxide film does not occur much, evenin an oxygen atmosphere, and no difference in effect was observedbetween an oxygen atmosphere and a nitrogen atmosphere. Further, in heattreatments in accordance with the present invention, it was ascertainedthat neither low-temperature process heat simulation norhigh-temperature process flow heat simulation had any affect on oxidefilm reliability or other quality factors related to an epitaxial wafer,making an atmosphere of oxygen, or nitrogen, or a gas mixture thereofdesirable.

EMBODIMENTS Embodiment 1

Six-inch outer diameter, p(100) B-doped (10 mΩ·cm resistivity) Cz-Siwafers, having initial oxygen concentrations of 12×10¹⁷ atoms/ cm³,13×10¹⁷ atoms/cm³, 14×10¹⁷ atoms/cm³, and 15×10¹⁷ atoms/cm³ (old ASTM)were prepared, heat treatments of 600° C.×5 hr., 650° C.×5 hr., 700°C.×1 hr., 700° C.×3 hr., 800° C.×1 hr., 800° C.×3 hr., 900° C.×3 hr.,and 950° C.×3 hr. were applied to these wafers in a nitrogen atmosphereprior to epitaxial layer growth, then these wafers, including wafersthat had not undergone heat treatment, were set inside a singlewafer-type CVD reactor at 850° C., the temperature was increased at arate of 150° C./minute to 1150° C., and following etching with HCl, a 3μm-thick epitaxial layer with a resistivity of 10Ω·cm was grown at 1050°C. using SiHCl₃ gas, to produce epitaxial wafers.

These epitaxial wafers were subjected to low-temperature process heatsimulation of the pattern shown in FIG. 1, and thereafter selectivelyetched (5 minute Wright Etch), and BMD measured using an opticalmicroscope. The results thereof are shown in FIG. 5.

As shown in FIG. 5, heat treatment at 600° C. for 5 hours, and at 950°C. for 3 hours did not achieve sufficient BMD, but BMD of 5×10⁴defects/cm² or higher, which is sufficient for gettering, was observedin those wafers that underwent pre-epitaxial growth heat treatment at650° C. for 5 hours, and at 700° C., 800° C., and 900° C. for 3 hours ina low-temperature process heat simulation of the pattern shown in FIG.1.

Further, epitaxial wafers with an initial oxygen concentration of15×10¹⁷ atoms/cm³, which had been subjected to pre-epitaxial growth heattreatment in a nitrogen atmosphere at 800° C. for 3 hours, were actuallycontaminated on purpose with Ni (1×10¹² atoms/cm²), following which theywere subjected to the same low-temperature process heat simulation.After simulation, generation lifetime measurements were performed inaccordance with the MOS-Ct method. The results thereof are shown in FIG.7.

Generation lifetime was good, with no apparent difference betweenpurposely contaminated and uncontaminated wafers, and in wafers that hadbeen subjected to appropriate pre-epitaxial growth heat treatment, asufficient gettering effect was confirmed in the low-temperatureprocess.

Embodiment 2

Eight-inch outer diameter, p(100) B-doped (10Ω·cm resistivity) Cz-Siwafers, having an initial oxygen concentration of 15×10¹⁷ atoms/cm³ (oldASTh), were prepared, and heat treatments of

1) 650° C.×3 hr., 650° C.×5 hr.,

2) 700° C.×1 hr., 700° C.×3 hr., 700° C.×5 hr.,

3) 750° C.×1 hr., 750° C.×2 hr., 750° C.×3 hr., 750° C.×5 hr.,

4) 800° C.×0.5 hr., 800° C.×1 hr., 800° C.×2 hr., 800° C.×3 hr., 800°C.×5 hr.,

5) 850° C.×0.5 hr., 850° C.×1 hr., 850° C.×2 hr., 850° C.×3 hr., 850°C.×5 hr.,

6) 900° C.×0.5 hr., 900° C.×3 hr., 900° C.×5 hr.,

7) 950° C.×0.5 hr., 950° C.×3 hr., 950° C.×5 hr.

were applied to these wafers in a nitrogen atmosphere prior to epitaxiallayer growth, then these wafers were set inside a single wafer-type CVDreactor at 850° C., the temperature was increased at a rate of 150°C./minute to 1150° C., and following etching with HCl, a 3 μm-thickepitaxial layer with a resistivity of 10Ω·cm was grown at 1050° C. usingSiHCl₃ gas, producing epitaxial wafers.

These epitaxial wafers were subjected to high-temperature process flowheat simulation of the pattern shown in FIG. 2, and thereafterselectively etched (5 minute Wright Etch), and BMD measured using anoptical microscope. The results thereof are shown in FIG. 6.

As shown in FIG. 6, pre-epitaxial growth heat treatment at 650° C. andat 950° C. for 5 hours did not achieve sufficient BMD, but BMD of 5×10⁴defects/cm² or higher, which is sufficient for gettering (IG), wasobserved in those wafers that underwent pre-epitaxial growth heattreatment at 700° C., 750° C., 800^(20 C.,) 850° C., and 900° C. for 3hours in a semiconductor device process high-temperature process flowheat simulation of the pattern shown in FIG. 2. However, BMD of 5×10⁵defects/cm² or higher was observed in wafers that had undergonepre-epitaxial growth heat treatment at 800° C. for 2 hours and 3 hours,and excess precipitation-caused dislocations were observed in the centerportion of wafers. The optimum region for BMD which is sufficient forgettering (IG), and which does not generate dislocations is 5×10⁴˜5×10⁵defects/cm².

Embodiment 3

Next, 8-inch outer diameter, p(100) B-doped (10Ω·cm resistivity) Cz-Siwafers, having an initial oxygen concentration in the range of13˜16×10¹⁷ atoms/cm³ (old ASTM), were prepared, and heat treatments at800° C.×2 hr. were applied to these wafers in a nitrogen atmosphereprior to an epitaxial layer growth process, then these wafers were setinside a single wafer-type CVD reactor at 850° C., the temperature wasincreased at a rate of 150° C./minute to 1150° C., and following etchingwith HCl, a 3 μm-thick epitaxial layer with a resistivity of 10Ω·cm wasgrown at 1050° C. using SiHCl₃ gas, producing epitaxial wafers.

These epitaxial wafers were subjected to high-temperature process flowheat simulation of the pattern shown in FIG. 2, and thereafterselectively etched (5 minute Wright Etch), and BMD measured using anoptical microscope. The results thereof are shown in FIG. 8.

As shown in FIG. 8, with pre-epitaxial growth heat treatment at 800° C.for 2 hours, the BMD density of CZ-Si wafers having an initial oxygenconcentration of 13.8×10¹⁷ atoms/cm³ (old ASTM) were within the optimumBMD region, and it was ascertained that no dislocations had beengenerated. However, with CZ-i wafers having an initial oxygenconcentration of 13.8×10¹⁷ atoms/cm³ (old ASTM), high density BMD wasgenerated, and slippage dislocations resulting from excess precipitationwere observed, similar to the results of FIG. 6. Therefore, when BMDdensity exceeds the upper limit in accordance with heat treatment withinthe scope of the present invention, it is possible to form BMD of anappropriate density by optimizing the initial oxygen concentration.

INDUSTRIAL APPLICABILITY

The present invention grants gettering capabilities to a 10 mΩ·cm orhigher resistivity, p-type (Bdoped) CDSi wafer, which cannot be expectedto produce a sufficient gettering effect (IG) in either alow-temperature device process or a high-temperature device process, andin accordance with applying a predetermined low-temperature heattreatment to an ingot pulled using the CZ method, or in accordance withapplying a suitable heat treatment prior to growing an epitaxial layerby selecting a heat treatment time according to the processingtemperature of a device manufacturing process, enables the generation ofsufficient BMD in both a low-temperature device process and ahigh-temperature device process, and makes possible sufficient getteringeven when heavy metal impurities occur in the process. Further, inaccordance with the heat treatment conditions of the present invention,it is possible to prevent the generation of in-process slippagedislocations resulting from excess oxygen precipitation.

Further, due to flatness problems, the specifications of next-generation12-inch wafers are expected to call for a mirror-polished finish on bothsides, and to grant PBS (Poly-Si Back Seal) or BSD (Back Side Damage) EG(Extrinsic Gettering) to the backside of a wafer will require a complexmanufacturing process. However, the present invention makes possible theuse of a simple process to grant sufficient gettering effect (IG effect)to an epitaxial wafer even when it is mirror polished on both sides.

Further, since a 1-step low-temperature heat treatment is sufficient toensure via an epitaxial layer the near-surface integrity of a deviceactive layer, there is no need for a high-temperature heat treatment,enabling heat treatment to be performed at a lower cost than the DZ-IGprocessing performed on ordinary CZ-Si wafers to date. For example, inthe above-described processing performed in an epitaxial reactor duringan epitaxial process (Japanese Patent Laid-open No. 8-97220), volumeprocessing is difficult, but since the method in accordance with thepresent invention is carried out using an ordinary annealing furnace, itis advantageous in that a large volume of wafers can be processed at onetime, and the throughput of the epitaxial growth process itself iscompletely unaffected.

What is claimed is:
 1. A semiconductor silicon epitaxial wafermanufacturing method, comprising applying a heat treatment at atemperature of between 650° C. and 900° C. in either an oxygen ornitrogen atmosphere or a mixed gas atmosphere thereof, to a 10 mΩ·cm orhigher substrate resistivity wherein the oxygen concentration is 10˜lessthan 14.4×10¹⁷ atoms/cm³ (old ASTM); and p-type (B-doped) CZ-Si wafer,BMD nuclei capable of generating BMD of 5×10⁴ defects/cm²˜5×10⁵defects/cm² are formed in a 1050° C. or lower temperature devicemanufacturing process, after which, the wafer is mirror polished oneither one side or two sides, and an epitaxial layer is grown on asurface using a vapor-phase growth method.
 2. A semiconductor siliconepitaxial wafer manufacturing method, comprising applying a heattreatment at a temperature of between 700° C. and 900° C. in either anoxygen or nitrogen atmosphere or a mixed gas atmosphere thereof, to a 10mΩ·cm or higher substrate resistivity wherein the oxygen concentrationis 10˜less than 14.4×10¹⁷ atoms/cm³ (old ASTM); and p-type (B-doped)CZ-Si wafer, BMD nuclei capable of generating BMD of 5×10⁴defects/cm²˜5×10⁵ defects/cm² are formed in a 1050° C. or highertemperature device manufacturing process, after which, the wafer ismirror polished on either one side or two sides, and an epitaxial layeris grown on a surface using a vapor-phase growth method.
 3. Asemiconductor silicon epitaxial wafer manufacturing method, comprisingapplying a heat treatment at a temperature of between 650° C. and 900°C. to a silicon single crystal ingot pulled and removed via the CZmethod by controlling the concentration of B so as to obtain a 10 mΩ·orhigher resistivity, p-type (B-doped) CZ-Si wafer, and without performinga process that would produce an EG effect after the ingot has beensliced into silicon wafers, BMD nuclei capable of forming BMD sufficientfor gettering are formed in a 1050° C. or lower temperature devicemanufacturing process, the wafer is mirror polished on either one sideor two sides, and an epitaxial layer is grown on a surface using avapor-phase growth method.
 4. The semiconductor silicon epitaxial wafermanufacturing method of claim 3 wherein the BMD density generated by thedevice manufacturing process is 5×10⁴ defects/cm²˜5×10⁵ defects/cm². 5.The semiconductor silicon epitaxial wafer manufacturing method accordingto claim 3, wherein the oxygen concentration of the ingot is 10˜15×10¹⁷atoms/cm³ (old ASTM).
 6. A semiconductor silicon epitaxial wafermanufacturing method, comprising applying a heat treatment at atemperature of between 700° C. and 900° C. to a silicon single crystalingot pulled and removed via the CZ method by controlling theconcentration of B so as to obtain 10 mΩ·cm or higher resistivity,p-type (B-doped) CZ-Si wafer, and without performing a process thatwould produce an EG effect after slicing the ingot into silicon wafers,BMD nuclei capable of forming BMD sufficient for gettering are formed ina 1050° C. or higher temperature device manufacturing process, the waferis mirror polished on either one side or two sides, and an epitaxiallayer is grown on a surface using a vapor-phase growth method.
 7. Thesemiconductor silicon epitaxial wafer manufacturing method of claim 6wherein the BMD density generated by the device manufacturing process is5×10⁴ defects/cm²˜5×10⁵ defects/cm².
 8. semiconductor silicon epitaxialwafer manufacturing method according to claim 6, wherein theconcentration of the ingot is 10˜15×10¹⁷ atoms/cm³ (old ASTM).